1. Field of the Invention
The present invention relates to semiconductor integrated circuit devices, particularly to a semiconductor integrated circuit device having an output buffer including an MOS transistor that receives voltage at its gate higher than supply voltage to discharge an output node.
2. Description of the Background Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) includes an output buffer for outputting an internal data signal to any external unit. A buffer of N--N type is usually used at the final stage of the output buffer. A power supply voltage Vcc is supplied to the gate of an N channel MOS transistor connected to the ground node for obtaining an output of an L (logical low) level from the N--N type buffer. In order to improve a pull-down characteristic of the output of such an output buffer, the size (gate width) of the N channel MOS transistor of the N--N type buffer should be increased.
With the recent miniaturization of semiconductor memory devices, an output buffer is implemented that can improve the pull-down characteristic of an output without increasing the size of the transistor as shown in FIG. 9.
Referring to FIG. 9 illustrating the output buffer, when an output enable signal OEM and a read data signal RD attain an H (logical high) level, the level of an output of an NAND circuit ND goes L and accordingly the level of an output of an inverter IV goes H. Further, an N channel MOS transistor NT is turned on and the level of a node N goes L. Consequently, a P channel MOS transistor PT connected to a boosted node Vpp having a voltage Vpp higher than power supply voltage Vcc is turned on and voltage Vpp is supplied to the gate of an N channel MOS transistor NTb. Accordingly, N channel MOS transistor NTb is turned on more speedily compared with the case in which supply voltage Vcc is supplied to the gate. The pull-down characteristic of the output is thus improved.
Although the fall time of an output DQ is shortened by supplying voltage Vpp higher than supply voltage Vcc to the gate of N channel MOS transistor NTb, the shortened fall time is likely to cause ringing. The influence of the ringing causes such problems as that a desired output voltage cannot be obtained and the access time is delayed.